@@ -4969,13 +4969,16 @@ typedef struct
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tmpreg = READ_BIT (RCC -> APB1ENR , RCC_APB1ENR_RTCAPBEN );\
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UNUSED (tmpreg ); \
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} while (0U )
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+ #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_USART3_CLK_ENABLE () do { \
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__IO uint32_t tmpreg = 0x00U; \
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SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
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/* Delay after an RCC peripheral clock enabling */ \
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tmpreg = READ_BIT (RCC -> APB1ENR , RCC_APB1ENR_USART3EN );\
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UNUSED (tmpreg ); \
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} while (0U )
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+ #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
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+
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#if defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_UART4_CLK_ENABLE () do { \
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__IO uint32_t tmpreg = 0x00U; \
@@ -5095,7 +5098,9 @@ typedef struct
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#endif /* STM32F413xx || STM32F423xx */
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#define __HAL_RCC_RTCAPB_CLK_DISABLE () (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
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#define __HAL_RCC_SPI3_CLK_DISABLE () (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
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+ #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_USART3_CLK_DISABLE () (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
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+ #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
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#if defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_UART4_CLK_DISABLE () (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
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#define __HAL_RCC_UART5_CLK_DISABLE () (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
@@ -5135,7 +5140,9 @@ typedef struct
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#endif /* STM32F413xx || STM32F423xx */
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#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED () ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
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#define __HAL_RCC_SPI3_IS_CLK_ENABLED () ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
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+ #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_USART3_IS_CLK_ENABLED () ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
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+ #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
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#if defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_UART4_IS_CLK_ENABLED () ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
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#define __HAL_RCC_UART5_IS_CLK_ENABLED () ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
@@ -5164,7 +5171,9 @@ typedef struct
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#endif /* STM32F413xx || STM32F423xx */
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#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED () ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
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#define __HAL_RCC_SPI3_IS_CLK_DISABLED () ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
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+ #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_USART3_IS_CLK_DISABLED () ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
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+ #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
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#if defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_UART4_IS_CLK_DISABLED () ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
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#define __HAL_RCC_UART5_IS_CLK_DISABLED () ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
@@ -5436,7 +5445,9 @@ typedef struct
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#define __HAL_RCC_LPTIM1_FORCE_RESET () (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
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#endif /* STM32F413xx || STM32F423xx */
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#define __HAL_RCC_SPI3_FORCE_RESET () (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
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+ #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_USART3_FORCE_RESET () (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
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+ #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
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#if defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_UART4_FORCE_RESET () (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
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#define __HAL_RCC_UART5_FORCE_RESET () (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
@@ -5464,7 +5475,9 @@ typedef struct
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#define __HAL_RCC_LPTIM1_RELEASE_RESET () (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
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#endif /* STM32F413xx || STM32F423xx */
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#define __HAL_RCC_SPI3_RELEASE_RESET () (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
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+ #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_USART3_RELEASE_RESET () (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
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+ #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
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#if defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_UART4_RELEASE_RESET () (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
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#define __HAL_RCC_UART5_RELEASE_RESET () (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
@@ -5620,7 +5633,9 @@ typedef struct
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#endif /* STM32F413xx || STM32F423xx */
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#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE () (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
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#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE () (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
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+ #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE () (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
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+ #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
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#if defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE () (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
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#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE () (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
@@ -5649,7 +5664,9 @@ typedef struct
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#endif /* STM32F413xx || STM32F423xx */
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#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE () (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
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#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE () (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
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+ #if defined(STM32F412Zx ) || defined(STM32F412Vx ) || defined(STM32F412Rx ) || defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE () (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
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+ #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
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#if defined(STM32F413xx ) || defined(STM32F423xx )
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#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE () (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
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#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE () (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
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