enabling IPCC module of the stm32WB55

to support BLE on this nucleo_wb55rg
Align Peripheral CLK Config on MBDED

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

variants/PNUCLEO_WB55RG/variant.cpp

@@ -138,6 +138,8 @@ WEAK void SystemClock_Config(void)
     Error_Handler();
   }
   /* Initializes the peripherals clocks */
+  /* from MBED:
+   * 
   PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_USB;
   PeriphClkInitStruct.PLLSAI1.PLLN = 24;
   PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2;
@@ -146,13 +148,34 @@ WEAK void SystemClock_Config(void)
   PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK;
   PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
   PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
-  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
+  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0; */
+  /* RNG needs to be configured like in M0 core, i.e. with HSI48 */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
+    PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+    PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+    PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+        Error_Handler();
+    }
+
+    LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+    LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+    // LL_PWR_SMPS_Enable();
+
+    /* Select HSI as system clock source after Wake Up from Stop mode */
+    LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
 
-  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
-    Error_Handler();
-  }
   /* Enable MSI Auto calibration */
   HAL_RCCEx_EnableMSIPLLMode();
+
+/* */
+LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+
+LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_MSI);
+
 }
 
 #ifdef __cplusplus

variants/PNUCLEO_WB55RG/variant.h

@@ -120,6 +120,9 @@ extern "C" {
 // for EEPROM emulation to the last 512k pages.
 #define FLASH_PAGE_NUMBER       127
 
+
+#define HAL_IPCC_MODULE_ENABLED
+
 #ifdef __cplusplus
 } // extern "C"
 #endif