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system(G0): update STM32G0xx CMSIS Drivers to v1.4.4
Included in STM32CubeG0 FW v1.6.2 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 471598d commit 213ec65

29 files changed

+176
-45
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h

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@@ -4045,6 +4045,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
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#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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4048+
#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
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#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
4050+
#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
4051+
#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
4052+
#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
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40484054
/*!< HPRE configuration */
40494055
#define RCC_CFGR_HPRE_Pos (8U)
40504056
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h

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@@ -4225,6 +4225,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
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#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
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#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
4230+
#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
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#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
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#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
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42284234
/*!< HPRE configuration */
42294235
#define RCC_CFGR_HPRE_Pos (8U)
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#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g041xx.h

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@@ -4461,6 +4461,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
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#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
4465+
#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
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#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
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#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
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#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
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44644470
/*!< HPRE configuration */
44654471
#define RCC_CFGR_HPRE_Pos (8U)
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#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g050xx.h

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@@ -4064,6 +4064,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
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#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
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#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
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#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
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#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
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#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
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40674073
/*!< HPRE configuration */
40684074
#define RCC_CFGR_HPRE_Pos (8U)
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#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g051xx.h

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@@ -4561,6 +4561,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
45624562
#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
4565+
#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
4566+
#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
4567+
#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
4568+
#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
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45644570
/*!< HPRE configuration */
45654571
#define RCC_CFGR_HPRE_Pos (8U)
45664572
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g061xx.h

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@@ -4797,6 +4797,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
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#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
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#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
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#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
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#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
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#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
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48004806
/*!< HPRE configuration */
48014807
#define RCC_CFGR_HPRE_Pos (8U)
48024808
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h

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@@ -4193,6 +4193,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
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#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
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#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
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#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
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#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
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#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
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41964202
/*!< HPRE configuration */
41974203
#define RCC_CFGR_HPRE_Pos (8U)
41984204
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h

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@@ -4896,6 +4896,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
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#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
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#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
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#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
4902+
#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
4903+
#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
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48994905
/*!< HPRE configuration */
49004906
#define RCC_CFGR_HPRE_Pos (8U)
49014907
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g081xx.h

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@@ -5132,6 +5132,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
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#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
5136+
#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
5137+
#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
5138+
#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
5139+
#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
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51355141
/*!< HPRE configuration */
51365142
#define RCC_CFGR_HPRE_Pos (8U)
51375143
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b0xx.h

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@@ -325,7 +325,7 @@ typedef struct
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typedef struct
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{
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__IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
328-
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
328+
__IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */
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__IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */
330330
__IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */
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__IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
@@ -4363,6 +4363,9 @@ typedef struct
43634363
#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
43644364
#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */
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4366+
#define PWR_CR2_USV_Pos (10U)
4367+
#define PWR_CR2_USV_Msk (0x1UL << PWR_CR2_USV_Pos) /*!< 0x00000400 */
4368+
#define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
43664369

43674370
/******************** Bit definition for PWR_CR3 register ********************/
43684371
#define PWR_CR3_EWUP_Pos (0U)
@@ -5162,6 +5165,12 @@ typedef struct
51625165
#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
51635166
#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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5168+
#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
5169+
#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
5170+
#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
5171+
#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
5172+
#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
5173+
51655174
/*!< HPRE configuration */
51665175
#define RCC_CFGR_HPRE_Pos (8U)
51675176
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0b1xx.h

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@@ -6146,6 +6146,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
61476147
#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
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6149+
#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
6150+
#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
6151+
#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
6152+
#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
6153+
#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
6154+
61496155
/*!< HPRE configuration */
61506156
#define RCC_CFGR_HPRE_Pos (8U)
61516157
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0c1xx.h

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@@ -6382,6 +6382,12 @@ typedef struct
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#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
63836383
#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
63846384

6385+
#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */
6386+
#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
6387+
#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */
6388+
#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
6389+
#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */
6390+
63856391
/*!< HPRE configuration */
63866392
#define RCC_CFGR_HPRE_Pos (8U)
63876393
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h

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*/
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#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
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#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
93-
#define __STM32G0_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
93+
#define __STM32G0_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
9494
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
9595
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
9696
|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/License.md renamed to ‎system/Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.md

File renamed without changes.

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md

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# STM32CubeG0 CMSIS Device MCU Component
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![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_g0.svg?color=brightgreen)
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## Overview
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57
**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
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7-
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
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* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
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* The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
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* The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
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* A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ...
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* A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
9+
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
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* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
11+
* The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
12+
* The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
13+
* A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
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* A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
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14-
Two models of publication are proposed for the STM32Cube embedded software :
15-
* The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
16-
* The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions.
16+
Two models of publication are proposed for the STM32Cube embedded software:
17+
* The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
18+
* The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
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## Description
1921

@@ -30,6 +32,5 @@ It is **crucial** that you use a consistent set of versions for the CMSIS Core -
3032
The full **STM32CubeG0** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG0).
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## Troubleshooting
33-
If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_g0/issues/new).
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35-
For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
36+
Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.

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