From b86d1a7e8fafd3de0b21912f78c37d3fdac34fa9 Mon Sep 17 00:00:00 2001
From: Nikita Popov <nikita.ppv@gmail.com>
Date: Fri, 12 Jul 2019 20:03:34 +0000
Subject: [PATCH 1/2] [SystemZ] Fix addcarry of addcarry of const carry
 (PR42606)

This fixes https://bugs.llvm.org/show_bug.cgi?id=42606 by extending
D64213. Instead of only checking if the carry comes from a matching
operation, we now check the full chain of carries. Otherwise we might
custom lower the outermost addcarry, but then generically legalize
an inner addcarry.

Differential Revision: https://reviews.llvm.org/D64658

llvm-svn: 365949
---
 .../Target/SystemZ/SystemZISelLowering.cpp    | 16 +++++++--
 llvm/test/CodeGen/SystemZ/pr42606.ll          | 35 +++++++++++++++++++
 2 files changed, 49 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/SystemZ/pr42606.ll

diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 56ec3a5b588d1..158cddedc9674 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -3427,6 +3427,18 @@ SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
   return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
 }
 
+static bool isAddCarryChain(SDValue Carry) {
+  while (Carry.getOpcode() == ISD::ADDCARRY)
+    Carry = Carry.getOperand(2);
+  return Carry.getOpcode() == ISD::UADDO;
+}
+
+static bool isSubBorrowChain(SDValue Carry) {
+  while (Carry.getOpcode() == ISD::SUBCARRY)
+    Carry = Carry.getOperand(2);
+  return Carry.getOpcode() == ISD::USUBO;
+}
+
 // Lower ADDCARRY/SUBCARRY nodes.
 SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
                                                 SelectionDAG &DAG) const {
@@ -3449,7 +3461,7 @@ SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
   switch (Op.getOpcode()) {
   default: llvm_unreachable("Unknown instruction!");
   case ISD::ADDCARRY:
-    if (Carry.getOpcode() != ISD::UADDO && Carry.getOpcode() != ISD::ADDCARRY)
+    if (!isAddCarryChain(Carry))
       return SDValue();
 
     BaseOp = SystemZISD::ADDCARRY;
@@ -3457,7 +3469,7 @@ SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
     CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
     break;
   case ISD::SUBCARRY:
-    if (Carry.getOpcode() != ISD::USUBO && Carry.getOpcode() != ISD::SUBCARRY)
+    if (!isSubBorrowChain(Carry))
       return SDValue();
 
     BaseOp = SystemZISD::SUBCARRY;
diff --git a/llvm/test/CodeGen/SystemZ/pr42606.ll b/llvm/test/CodeGen/SystemZ/pr42606.ll
new file mode 100644
index 0000000000000..c3602de73b9bb
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/pr42606.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+define i64 @test(i64 %lo, i64 %hi) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    la %r0, 0(%r2,%r2)
+; CHECK-NEXT:    clgr %r0, %r2
+; CHECK-NEXT:    ipm %r0
+; CHECK-NEXT:    la %r1, 1(%r2,%r2)
+; CHECK-NEXT:    cghi %r1, 0
+; CHECK-NEXT:    ipm %r1
+; CHECK-NEXT:    afi %r1, -268435456
+; CHECK-NEXT:    srl %r1, 31
+; CHECK-NEXT:    rosbg %r1, %r0, 63, 63, 36
+; CHECK-NEXT:    algfr %r3, %r1
+; CHECK-NEXT:    lgr %r2, %r3
+; CHECK-NEXT:    br %r14
+  %tmp = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %lo, i64 1)
+  %tmp1 = extractvalue { i64, i1 } %tmp, 0
+  %tmp2 = extractvalue { i64, i1 } %tmp, 1
+  %tmp3 = zext i1 %tmp2 to i64
+  %tmp4 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %lo, i64 %tmp1)
+  %tmp5 = extractvalue { i64, i1 } %tmp4, 1
+  %tmp6 = zext i1 %tmp5 to i64
+  %spec.select.i = add i64 0, %hi
+  %tmp7 = add i64 %spec.select.i, %tmp3
+  %tmp8 = add i64 %tmp7, %tmp6
+  ret i64 %tmp8
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) #0
+
+attributes #0 = { nounwind readnone speculatable }

From 666c7d1a6d424e93e1e4c41d0888e3626576014b Mon Sep 17 00:00:00 2001
From: Nikita Popov <nikita.ppv@gmail.com>
Date: Fri, 12 Jul 2019 20:52:02 +0000
Subject: [PATCH 2/2] [builtins] Fix assembly in arm sync-ops.h

This assembly is part of a macro that was reformatted in D60351.
The missing space between push and { results in:

    Error: bad instruction `push{r4, r5,r6,lr}'

llvm-svn: 365957
---
 compiler-rt/lib/builtins/arm/sync-ops.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler-rt/lib/builtins/arm/sync-ops.h b/compiler-rt/lib/builtins/arm/sync-ops.h
index 5bb863d8cf98a..c9623249e5d20 100644
--- a/compiler-rt/lib/builtins/arm/sync-ops.h
+++ b/compiler-rt/lib/builtins/arm/sync-ops.h
@@ -34,7 +34,7 @@
   .thumb;                                                                      \
   .syntax unified;                                                             \
   DEFINE_COMPILERRT_THUMB_FUNCTION(__sync_fetch_and_##op)                      \
-  push{r4, r5, r6, lr};                                                        \
+  push {r4, r5, r6, lr};                                                       \
   dmb;                                                                         \
   mov r12, r0;                                                                 \
   LOCAL_LABEL(tryatomic_##op) : ldrexd r0, r1, [r12];                          \