rebuilding FSP for portentac33 in order to set RTC_CFG_OPEN_SET_CLOCK_SOURCE to 0

Author: pennam

extras/e2studioProjects/portenta_h33_lib/configuration.xml

@@ -1074,7 +1074,7 @@
     </config>
     <config id="config.driver.rtc">
       <property id="config.driver.rtc.param_checking_enable" value="config.driver.rtc.param_checking_enable.bsp"/>
-      <property id="config.driver.rtc.open_set_source_clock" value="config.driver.rtc.open_set_source_clock.enabled"/>
+      <property id="config.driver.rtc.open_set_source_clock" value="config.driver.rtc.open_set_source_clock.disabled"/>
     </config>
     <config id="config.driver.spi">
       <property id="config.driver.spi.param_checking_enable" value="config.driver.spi.param_checking_enable.bsp"/>

extras/e2studioProjects/portenta_h33_lib/ra_cfg.txt

@@ -341,8 +341,8 @@ FSP Configuration
     Reception: FIFOs: FIFO 7: Interrupt Threshold: 1/2 full
     Reception: FIFOs: FIFO 7: Payload Size: 8 bytes
     Reception: FIFOs: FIFO 7: Depth: 16 stages
-    Reception: Acceptance Filtering: Channel 0 Rule Count: 1
-    Reception: Acceptance Filtering: Channel 1 Rule Count: 1
+    Reception: Acceptance Filtering: Channel 0 Rule Count: 2
+    Reception: Acceptance Filtering: Channel 1 Rule Count: 2
 
   Module "I2C Master (r_iic_master)"
     Parameter Checking: Default (BSP)
@@ -408,7 +408,7 @@ FSP Configuration
 
   Module "Flash (r_flash_hp)"
     Parameter Checking: Default (BSP)
-    Code Flash Programming Enable: Disabled
+    Code Flash Programming Enable: Enabled
     Data Flash Programming Enable: Enabled
 
   Module "USB PCDC (r_usb_pcdc)"
@@ -442,7 +442,7 @@ FSP Configuration
 
   Module "Realtime Clock (r_rtc)"
     Parameter Checking: Default (BSP)
-    Set Source Clock in Open: Enabled
+    Set Source Clock in Open: Disabled
 
   Module "Timer, General PWM (r_gpt)"
     Parameter Checking: Default (BSP)

variants/PORTENTA_C33/includes/ra_cfg/fsp_cfg/r_rtc_cfg.h

@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 #define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-#define RTC_CFG_OPEN_SET_CLOCK_SOURCE (1)
+#define RTC_CFG_OPEN_SET_CLOCK_SOURCE (0)
 
 #ifdef __cplusplus
 }